1. Technical Field
The present invention relates to a system and method for re-shuffling test case instruction orders for processor design verification and validation. More particularly, the present invention relates to a system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
Verifying and validating a processor using test cases typically includes three stages, which are 1) test pattern build stage, 2) test pattern execution stage, and 3) validation and verification stage. A challenge found is that a large amount of test cases are usually generated in order to sufficiently test a processor. Unfortunately, this consumes a tremendous amount of upfront time, which leaves little time to test the processor.
What is needed, therefore, is a system and method for efficiently testing a processor without spending a large amount of time generating test cases.